E203译码模块(3)
E203 译码模块(1)E203 译码模块(2)E203 译码模块(3)下面的代码译码出指令的立即数，不同的指令有不同的立即数编码形式。
//I类型指令的imm，，符号位扩展成32位。
wire rv32_i_imm = {
{20{rv32_instr}}
, rv32_instr
};
//S类型指令的立即数
wire rv32_s_imm = {
{20{rv32_instr}}
, rv32_instr
, rv32_instr
};
//B类型指令的立即数
wire rv32_b_imm = {
{19{rv32_instr}}
, rv32_instr
, rv32_instr
, rv32_instr
, rv32_instr
, 1'b0
};
//U类型指令立即数
wire rv32_u_imm = {rv32_instr,12'b0};
//J类型指令立即数
wire rv32_j_imm = {
{11{rv32_instr}}
, rv32_instr
, rv32_instr
, rv32_instr
, rv32_instr
, 1'b0
};
// It will select i-type immediate when
// * rv32_op_imm
// * rv32_jalr
// * rv32_load
wire rv32_imm_sel_i = rv32_op_imm | rv32_jalr | rv32_load;
wire rv32_imm_sel_jalr = rv32_jalr;
wire rv32_jalr_imm = rv32_i_imm;
// It will select u-type immediate when
// * rv32_lui, rv32_auipc
wire rv32_imm_sel_u = rv32_lui | rv32_auipc;
// It will select j-type immediate when
// * rv32_jal
wire rv32_imm_sel_j = rv32_jal;
wire rv32_imm_sel_jal = rv32_jal;
wire rv32_jal_imm = rv32_j_imm;
// It will select b-type immediate when
// * rv32_branch
wire rv32_imm_sel_b = rv32_branch;
wire rv32_imm_sel_bxx = rv32_branch;
wire rv32_bxx_imm = rv32_b_imm;
// It will select s-type immediate when
// * rv32_store
wire rv32_imm_sel_s = rv32_store;以下是16位指令的立即数译码，16位指令立即数比较复杂。
// * Note: this CIS/CILI/CILUI/CI16SP-type is named by myself, because in
// ISA doc, the CI format for LWSP is different
// with other CI formats in terms of immediate
// It will select CIS-type immediate when
// * rv16_lwsp
wire rv16_imm_sel_cis = rv16_lwsp;
wire rv16_cis_imm ={
24'b0
, rv16_instr
, rv16_instr
, rv16_instr
, 2'b0
};
wire rv16_cis_d_imm ={
23'b0
, rv16_instr
, rv16_instr
, rv16_instr
, 3'b0
};
// It will select CILI-type immediate when
// * rv16_li
// * rv16_addi
// * rv16_slli
// * rv16_srai
// * rv16_srli
// * rv16_andi
wire rv16_imm_sel_cili = rv16_li | rv16_addi | rv16_slli
| rv16_srai | rv16_srli | rv16_andi;
wire rv16_cili_imm ={
{26{rv16_instr}}
, rv16_instr
, rv16_instr
};
// It will select CILUI-type immediate when
// * rv16_lui
wire rv16_imm_sel_cilui = rv16_lui;
wire rv16_cilui_imm ={
{14{rv16_instr}}
, rv16_instr
, rv16_instr
, 12'b0
};
// It will select CI16SP-type immediate when
// * rv16_addi16sp
wire rv16_imm_sel_ci16sp = rv16_addi16sp;
wire rv16_ci16sp_imm ={
{22{rv16_instr}}
, rv16_instr
, rv16_instr
, rv16_instr
, rv16_instr
, rv16_instr
, rv16_instr
, 4'b0
};
// It will select CSS-type immediate when
// * rv16_swsp
wire rv16_imm_sel_css = rv16_swsp;
wire rv16_css_imm ={
24'b0
, rv16_instr
, rv16_instr
, 2'b0
};
wire rv16_css_d_imm ={
23'b0
, rv16_instr
, rv16_instr
, 3'b0
};
// It will select CIW-type immediate when
// * rv16_addi4spn
wire rv16_imm_sel_ciw = rv16_addi4spn;
wire rv16_ciw_imm ={
22'b0
, rv16_instr
, rv16_instr
, rv16_instr
, rv16_instr
, rv16_instr
, 2'b0
};
// It will select CL-type immediate when
// * rv16_lw
wire rv16_imm_sel_cl = rv16_lw;
wire rv16_cl_imm ={
25'b0
, rv16_instr
, rv16_instr
, rv16_instr
, rv16_instr
, rv16_instr
, 2'b0
};
wire rv16_cl_d_imm ={
24'b0
, rv16_instr
, rv16_instr
, rv16_instr
, rv16_instr
, rv16_instr
, 3'b0
};
// It will select CS-type immediate when
// * rv16_sw
wire rv16_imm_sel_cs = rv16_sw;
wire rv16_cs_imm ={
25'b0
, rv16_instr
, rv16_instr
, rv16_instr
, rv16_instr
, rv16_instr
, 2'b0
};
wire rv16_cs_d_imm ={
24'b0
, rv16_instr
, rv16_instr
, rv16_instr
, rv16_instr
, rv16_instr
, 3'b0
};
// It will select CB-type immediate when
// * rv16_beqz
// * rv16_bnez
wire rv16_imm_sel_cb = rv16_beqz | rv16_bnez;
wire rv16_cb_imm ={
{23{rv16_instr}}
, rv16_instr
, rv16_instr
, rv16_instr
, rv16_instr
, rv16_instr
, 1'b0
};
wire rv16_bxx_imm = rv16_cb_imm;
// It will select CJ-type immediate when
// * rv16_j
// * rv16_jal
wire rv16_imm_sel_cj = rv16_j | rv16_jal;
wire rv16_cj_imm ={
{20{rv16_instr}}
, rv16_instr
, rv16_instr
, rv16_instr
, rv16_instr
, rv16_instr
, rv16_instr
, rv16_instr
, rv16_instr
, 1'b0
};
wire rv16_jjal_imm = rv16_cj_imm;
// It will select CR-type register (no-imm) when
// * rv16_jalr_mv_add
wire rv16_jrjalr_imm = 32'b0;
// It will select CSR-type register (no-imm) when
// * rv16_subxororand//wire rv32_load_fp_imm= rv32_i_imm;
//wire rv32_store_fp_imm = rv32_s_imm;
//以下代码是通过and or逻辑实现的5路并行多路选择器
wire rv32_imm =
({32{rv32_imm_sel_i}} & rv32_i_imm)
| ({32{rv32_imm_sel_s}} & rv32_s_imm)
| ({32{rv32_imm_sel_b}} & rv32_b_imm)
| ({32{rv32_imm_sel_u}} & rv32_u_imm)
| ({32{rv32_imm_sel_j}} & rv32_j_imm)
;
wirerv32_need_imm =
rv32_imm_sel_i
| rv32_imm_sel_s
| rv32_imm_sel_b
| rv32_imm_sel_u
| rv32_imm_sel_j
;
//以下是10输入并行多路选择器，根据不同的立即数类型，选择生成16位指令的最终立即数。
wire rv16_imm =
({32{rv16_imm_sel_cis }} & rv16_cis_imm)
| ({32{rv16_imm_sel_cili}} & rv16_cili_imm)
| ({32{rv16_imm_sel_cilui }} & rv16_cilui_imm)
| ({32{rv16_imm_sel_ci16sp}} & rv16_ci16sp_imm)
| ({32{rv16_imm_sel_css }} & rv16_css_imm)
| ({32{rv16_imm_sel_ciw }} & rv16_ciw_imm)
| ({32{rv16_imm_sel_cl }} & rv16_cl_imm)
| ({32{rv16_imm_sel_cs }} & rv16_cs_imm)
| ({32{rv16_imm_sel_cb }} & rv16_cb_imm)
| ({32{rv16_imm_sel_cj }} & rv16_cj_imm)
;
wire rv16_need_imm =
rv16_imm_sel_cis
| rv16_imm_sel_cili
| rv16_imm_sel_cilui
| rv16_imm_sel_ci16sp
| rv16_imm_sel_css
| rv16_imm_sel_ciw
| rv16_imm_sel_cl
| rv16_imm_sel_cs
| rv16_imm_sel_cb
| rv16_imm_sel_cj
;
assign need_imm = rv32 ? rv32_need_imm : rv16_need_imm;
//根据是rv32还是rv16，产生最终的立即数
assign dec_imm = rv32 ? rv32_imm : rv16_imm;
assign dec_pc= i_pc;
// 根据指令类型，产生最终的信息总线。
assign dec_info =
({`E203_DECINFO_WIDTH{alu_op}} & {{`E203_DECINFO_WIDTH-`E203_DECINFO_ALU_WIDTH{1'b0}},alu_info_bus})
| ({`E203_DECINFO_WIDTH{amoldst_op}} & {{`E203_DECINFO_WIDTH-`E203_DECINFO_AGU_WIDTH{1'b0}},agu_info_bus})
| ({`E203_DECINFO_WIDTH{bjp_op}} & {{`E203_DECINFO_WIDTH-`E203_DECINFO_BJP_WIDTH{1'b0}},bjp_info_bus})
| ({`E203_DECINFO_WIDTH{csr_op}} & {{`E203_DECINFO_WIDTH-`E203_DECINFO_CSR_WIDTH{1'b0}},csr_info_bus})
| ({`E203_DECINFO_WIDTH{muldiv_op}}& {{`E203_DECINFO_WIDTH-`E203_DECINFO_CSR_WIDTH{1'b0}},muldiv_info_bus})
;
wire legl_ops =
alu_op
| amoldst_op
| bjp_op
| csr_op
| muldiv_op
;解码16位指令的寄存器。
// To decode the registers for Rv16, divided into 8 groups
wire rv16_format_cr= rv16_jalr_mv_add;
wire rv16_format_ci= rv16_lwsp | rv16_flwsp | rv16_fldsp | rv16_li | rv16_lui_addi16sp | rv16_addi | rv16_slli;
wire rv16_format_css = rv16_swsp | rv16_fswsp | rv16_fsdsp;
wire rv16_format_ciw = rv16_addi4spn;
wire rv16_format_cl= rv16_lw | rv16_flw | rv16_fld;
wire rv16_format_cs= rv16_sw | rv16_fsw | rv16_fsd | rv16_subxororand;
wire rv16_format_cb= rv16_beqz | rv16_bnez | rv16_srli | rv16_srai | rv16_andi;
wire rv16_format_cj= rv16_j | rv16_jal;
// In CR Cases:
// * JR: rs1= rs1(coded), rs2= x0 (coded), rd = x0 (implicit)
// * JALR: rs1= rs1(coded), rs2= x0 (coded), rd = x1 (implicit)
// * MV: rs1= x0 (implicit),rs2= rs2(coded), rd = rd (coded)
// * ADD: rs1= rs1(coded), rs2= rs2(coded), rd = rd (coded)
// * eBreak: rs1= rs1(coded), rs2= x0 (coded), rd = x0 (coded)
wire rv16_need_cr_rs1 = rv16_format_cr & 1'b1;
wire rv16_need_cr_rs2 = rv16_format_cr & 1'b1;
wire rv16_need_cr_rd = rv16_format_cr & 1'b1;
wire [`E203_RFIDX_WIDTH-1:0] rv16_cr_rs1 = rv16_mv ? `E203_RFIDX_WIDTH'd0 : rv16_rs1[`E203_RFIDX_WIDTH-1:0];
wire [`E203_RFIDX_WIDTH-1:0] rv16_cr_rs2 = rv16_rs2[`E203_RFIDX_WIDTH-1:0];
// The JALR and JR difference in encoding is just the rv16_instr
wire [`E203_RFIDX_WIDTH-1:0] rv16_cr_rd= (rv16_jalr | rv16_jr)?
{{`E203_RFIDX_WIDTH-1{1'b0}},rv16_instr} : rv16_rd[`E203_RFIDX_WIDTH-1:0];
// In CI Cases:
// * LWSP: rs1= x2 (implicit),rd = rd
// * LI/LUI: rs1= x0 (implicit),rd = rd
// * ADDI: rs1= rs1(implicit),rd = rd
// * ADDI16SP: rs1= rs1(implicit),rd = rd
// * SLLI: rs1= rs1(implicit),rd = rd
wire rv16_need_ci_rs1 = rv16_format_ci & 1'b1;
wire rv16_need_ci_rs2 = rv16_format_ci & 1'b0;
wire rv16_need_ci_rd = rv16_format_ci & 1'b1;
wire [`E203_RFIDX_WIDTH-1:0] rv16_ci_rs1 = (rv16_lwsp | rv16_flwsp | rv16_fldsp) ? `E203_RFIDX_WIDTH'd2 :
(rv16_li | rv16_lui) ? `E203_RFIDX_WIDTH'd0 : rv16_rs1[`E203_RFIDX_WIDTH-1:0];
wire [`E203_RFIDX_WIDTH-1:0] rv16_ci_rs2 = `E203_RFIDX_WIDTH'd0;
wire [`E203_RFIDX_WIDTH-1:0] rv16_ci_rd= rv16_rd[`E203_RFIDX_WIDTH-1:0];
// In CSS Cases:
// * SWSP: rs1 = x2 (implicit), rs2= rs2
wire rv16_need_css_rs1= rv16_format_css & 1'b1;
wire rv16_need_css_rs2= rv16_format_css & 1'b1;
wire rv16_need_css_rd = rv16_format_css & 1'b0;
wire [`E203_RFIDX_WIDTH-1:0] rv16_css_rs1 = `E203_RFIDX_WIDTH'd2;
wire [`E203_RFIDX_WIDTH-1:0] rv16_css_rs2 = rv16_rs2[`E203_RFIDX_WIDTH-1:0];
wire [`E203_RFIDX_WIDTH-1:0] rv16_css_rd= `E203_RFIDX_WIDTH'd0;
// In CIW cases:
// * ADDI4SPN: rdd = rdd, rss1= x2 (implicit)
wire rv16_need_ciw_rss1 = rv16_format_ciw & 1'b1;
wire rv16_need_ciw_rss2 = rv16_format_ciw & 1'b0;
wire rv16_need_ciw_rdd= rv16_format_ciw & 1'b1;
wire [`E203_RFIDX_WIDTH-1:0] rv16_ciw_rss1= `E203_RFIDX_WIDTH'd2;
wire [`E203_RFIDX_WIDTH-1:0] rv16_ciw_rss2= `E203_RFIDX_WIDTH'd0;
wire [`E203_RFIDX_WIDTH-1:0] rv16_ciw_rdd= rv16_rdd[`E203_RFIDX_WIDTH-1:0];
// In CL cases:
// * LW: rss1 = rss1, rdd= rdd
wire rv16_need_cl_rss1= rv16_format_cl & 1'b1;
wire rv16_need_cl_rss2= rv16_format_cl & 1'b0;
wire rv16_need_cl_rdd = rv16_format_cl & 1'b1;
wire [`E203_RFIDX_WIDTH-1:0] rv16_cl_rss1 = rv16_rss1[`E203_RFIDX_WIDTH-1:0];
wire [`E203_RFIDX_WIDTH-1:0] rv16_cl_rss2 = `E203_RFIDX_WIDTH'd0;
wire [`E203_RFIDX_WIDTH-1:0] rv16_cl_rdd= rv16_rdd[`E203_RFIDX_WIDTH-1:0];
// In CS cases:
// * SW: rdd = none(implicit), rss1= rss1 , rss2=rss2
// * SUBXORORAND: rdd = rss1, rss1= rss1(coded), rss2=rss2
wire rv16_need_cs_rss1= rv16_format_cs & 1'b1;
wire rv16_need_cs_rss2= rv16_format_cs & 1'b1;
wire rv16_need_cs_rdd = rv16_format_cs & rv16_subxororand;
wire [`E203_RFIDX_WIDTH-1:0] rv16_cs_rss1 = rv16_rss1[`E203_RFIDX_WIDTH-1:0];
wire [`E203_RFIDX_WIDTH-1:0] rv16_cs_rss2 = rv16_rss2[`E203_RFIDX_WIDTH-1:0];
wire [`E203_RFIDX_WIDTH-1:0] rv16_cs_rdd= rv16_rss1[`E203_RFIDX_WIDTH-1:0];
// In CB cases:
// * BEQ/BNE: rdd = none(implicit), rss1= rss1, rss2=x0(implicit)
// * SRLI/SRAI/ANDI: rdd = rss1 , rss1= rss1, rss2=none(implicit)
wire rv16_need_cb_rss1= rv16_format_cb & 1'b1;
wire rv16_need_cb_rss2= rv16_format_cb & (rv16_beqz | rv16_bnez);
wire rv16_need_cb_rdd = rv16_format_cb & (~(rv16_beqz | rv16_bnez));
wire [`E203_RFIDX_WIDTH-1:0] rv16_cb_rss1 = rv16_rss1[`E203_RFIDX_WIDTH-1:0];
wire [`E203_RFIDX_WIDTH-1:0] rv16_cb_rss2 = `E203_RFIDX_WIDTH'd0;
wire [`E203_RFIDX_WIDTH-1:0] rv16_cb_rdd= rv16_rss1[`E203_RFIDX_WIDTH-1:0];
// In CJ cases:
// * J: rdd = x0(implicit)
// * JAL: rdd = x1(implicit)
wire rv16_need_cj_rss1= rv16_format_cj & 1'b0;
wire rv16_need_cj_rss2= rv16_format_cj & 1'b0;
wire rv16_need_cj_rdd = rv16_format_cj & 1'b1;
wire [`E203_RFIDX_WIDTH-1:0] rv16_cj_rss1 = `E203_RFIDX_WIDTH'd0;
wire [`E203_RFIDX_WIDTH-1:0] rv16_cj_rss2 = `E203_RFIDX_WIDTH'd0;
wire [`E203_RFIDX_WIDTH-1:0] rv16_cj_rdd= rv16_j ? `E203_RFIDX_WIDTH'd0 : `E203_RFIDX_WIDTH'd1;
// rv16_format_cr
// rv16_format_ci
// rv16_format_css
// rv16_format_ciw
// rv16_format_cl
// rv16_format_cs
// rv16_format_cb
// rv16_format_cj
wire rv16_need_rs1 = rv16_need_cr_rs1 | rv16_need_ci_rs1 | rv16_need_css_rs1;
wire rv16_need_rs2 = rv16_need_cr_rs2 | rv16_need_ci_rs2 | rv16_need_css_rs2;
wire rv16_need_rd= rv16_need_cr_rd| rv16_need_ci_rd| rv16_need_css_rd;
wire rv16_need_rss1 = rv16_need_ciw_rss1|rv16_need_cl_rss1|rv16_need_cs_rss1|rv16_need_cb_rss1|rv16_need_cj_rss1;
wire rv16_need_rss2 = rv16_need_ciw_rss2|rv16_need_cl_rss2|rv16_need_cs_rss2|rv16_need_cb_rss2|rv16_need_cj_rss2;
wire rv16_need_rdd= rv16_need_ciw_rdd |rv16_need_cl_rdd |rv16_need_cs_rdd |rv16_need_cb_rdd |rv16_need_cj_rdd ;
wire rv16_rs1en = (rv16_need_rs1 | rv16_need_rss1);
wire rv16_rs2en = (rv16_need_rs2 | rv16_need_rss2);
wire rv16_rden= (rv16_need_rd| rv16_need_rdd );
wire [`E203_RFIDX_WIDTH-1:0] rv16_rs1idx;
wire [`E203_RFIDX_WIDTH-1:0] rv16_rs2idx;
wire [`E203_RFIDX_WIDTH-1:0] rv16_rdidx ;
assign rv16_rs1idx =
({`E203_RFIDX_WIDTH{rv16_need_cr_rs1 }} & rv16_cr_rs1)
| ({`E203_RFIDX_WIDTH{rv16_need_ci_rs1 }} & rv16_ci_rs1)
| ({`E203_RFIDX_WIDTH{rv16_need_css_rs1}} & rv16_css_rs1)
| ({`E203_RFIDX_WIDTH{rv16_need_ciw_rss1}} & rv16_ciw_rss1)
| ({`E203_RFIDX_WIDTH{rv16_need_cl_rss1}}& rv16_cl_rss1)
| ({`E203_RFIDX_WIDTH{rv16_need_cs_rss1}}& rv16_cs_rss1)
| ({`E203_RFIDX_WIDTH{rv16_need_cb_rss1}}& rv16_cb_rss1)
| ({`E203_RFIDX_WIDTH{rv16_need_cj_rss1}}& rv16_cj_rss1)
;
assign rv16_rs2idx =
({`E203_RFIDX_WIDTH{rv16_need_cr_rs2 }} & rv16_cr_rs2)
| ({`E203_RFIDX_WIDTH{rv16_need_ci_rs2 }} & rv16_ci_rs2)
| ({`E203_RFIDX_WIDTH{rv16_need_css_rs2}} & rv16_css_rs2)
| ({`E203_RFIDX_WIDTH{rv16_need_ciw_rss2}} & rv16_ciw_rss2)
| ({`E203_RFIDX_WIDTH{rv16_need_cl_rss2}}& rv16_cl_rss2)
| ({`E203_RFIDX_WIDTH{rv16_need_cs_rss2}}& rv16_cs_rss2)
| ({`E203_RFIDX_WIDTH{rv16_need_cb_rss2}}& rv16_cb_rss2)
| ({`E203_RFIDX_WIDTH{rv16_need_cj_rss2}}& rv16_cj_rss2)
;
assign rv16_rdidx =
({`E203_RFIDX_WIDTH{rv16_need_cr_rd }} & rv16_cr_rd)
| ({`E203_RFIDX_WIDTH{rv16_need_ci_rd }} & rv16_ci_rd)
| ({`E203_RFIDX_WIDTH{rv16_need_css_rd}} & rv16_css_rd)
| ({`E203_RFIDX_WIDTH{rv16_need_ciw_rdd}} & rv16_ciw_rdd)
| ({`E203_RFIDX_WIDTH{rv16_need_cl_rdd}}& rv16_cl_rdd)
| ({`E203_RFIDX_WIDTH{rv16_need_cs_rdd}}& rv16_cs_rdd)
| ({`E203_RFIDX_WIDTH{rv16_need_cb_rdd}}& rv16_cb_rdd)
| ({`E203_RFIDX_WIDTH{rv16_need_cj_rdd}}& rv16_cj_rdd)
;
assign dec_rs1idx = rv32 ? rv32_rs1[`E203_RFIDX_WIDTH-1:0] : rv16_rs1idx;
assign dec_rs2idx = rv32 ? rv32_rs2[`E203_RFIDX_WIDTH-1:0] : rv16_rs2idx;
assign dec_rdidx= rv32 ? rv32_rd [`E203_RFIDX_WIDTH-1:0] : rv16_rdidx ;
assign dec_rs1en = rv32 ? rv32_need_rs1 : (rv16_rs1en & (~(rv16_rs1idx == `E203_RFIDX_WIDTH'b0)));
assign dec_rs2en = rv32 ? rv32_need_rs2 : (rv16_rs2en & (~(rv16_rs2idx == `E203_RFIDX_WIDTH'b0)));
assign dec_rdwen = rv32 ? rv32_need_rd: (rv16_rden& (~(rv16_rdidx== `E203_RFIDX_WIDTH'b0)));
assign dec_rs1x0 = (dec_rs1idx == `E203_RFIDX_WIDTH'b0);
assign dec_rs2x0 = (dec_rs2idx == `E203_RFIDX_WIDTH'b0);
wire rv_index_ilgl;
`ifdef E203_RFREG_NUM_IS_4 //{
assign rv_index_ilgl =
(| dec_rs1idx[`E203_RFIDX_WIDTH-1:2])
|(| dec_rs2idx[`E203_RFIDX_WIDTH-1:2])
|(| dec_rdidx [`E203_RFIDX_WIDTH-1:2])
;
`endif//}
`ifdef E203_RFREG_NUM_IS_8 //{
assign rv_index_ilgl =
(| dec_rs1idx[`E203_RFIDX_WIDTH-1:3])
|(| dec_rs2idx[`E203_RFIDX_WIDTH-1:3])
|(| dec_rdidx [`E203_RFIDX_WIDTH-1:3])
;
`endif//}
`ifdef E203_RFREG_NUM_IS_16 //{
assign rv_index_ilgl =
(| dec_rs1idx[`E203_RFIDX_WIDTH-1:4])
|(| dec_rs2idx[`E203_RFIDX_WIDTH-1:4])
|(| dec_rdidx [`E203_RFIDX_WIDTH-1:4])
;
`endif//}
`ifdef E203_RFREG_NUM_IS_32 //{
//Never happen this illegal exception
assign rv_index_ilgl = 1'b0;
`endif//}
assign dec_rv32 = rv32;
assign dec_bjp_imm =
({32{rv16_jal | rv16_j }} & rv16_jjal_imm)
| ({32{rv16_jalr_mv_add }} & rv16_jrjalr_imm)
| ({32{rv16_beqz | rv16_bnez }} & rv16_bxx_imm)
| ({32{rv32_jal }} & rv32_jal_imm)
| ({32{rv32_jalr }} & rv32_jalr_imm)
| ({32{rv32_branch }} & rv32_bxx_imm)
;
assign dec_jalr_rs1idx = rv32 ? rv32_rs1[`E203_RFIDX_WIDTH-1:0] : rv16_rs1[`E203_RFIDX_WIDTH-1:0];
assign dec_misalgn = i_misalgn;
assign dec_buserr= i_buserr ;
assign dec_ilegl =
(rv_all0s1s_ilgl)
| (rv_index_ilgl)
| (rv16_addi16sp_ilgl)
| (rv16_addi4spn_ilgl)
| (rv16_li_lui_ilgl)
| (rv16_sxxi_shamt_ilgl)
| (rv32_sxxi_shamt_ilgl)
| (rv32_dret_ilgl)
| (rv16_lwsp_ilgl)
| (~legl_ops);
完
页:
[1]