开源硬件（Risc-V）在教学环境中的应用
本帖最后由 小飞飞 于 2020-8-10 16:42 编辑这是一篇来自“All about circuits”的文章，作者基于其团队在过去5年PUPL项目的探索，分享了在学术环境中如何使用开源硬件尤其是RISC-V的话题，觉得非常有价值，推荐给大家阅读。
以下是原文并以蓝色加了部分注释： Utilizing Open Source Hardware in Academic Environments
In this article, Frank K Gürkaynak of ETH Zurich explores and explains his team's process of choosing and utilizing the open-source hardware platform RISC-V in an academic environment. Five years ago we started the Parallel Ultra Low Power (PULP) project at ETH Zürich together with the University of Bologna under the leadership of Luca Benini. Our goal was to explore novel computing architectures that are able to get the most out of the energy the system uses over a wide operational range starting from tiny systems used in the internet of things (IoT) all the way up to applications in high-performance computing (HPC). It was clear for us that to build such a system we would need a small but efficient processor core. But where to find such a processor core that we could use?
* 5年前的项目（PULP - 并行超低功耗）目标是选用一款精悍的内核做一种创新的计算架构以支持从IoT应用的微小系统到高性能计算较宽范围，都能比较省电。
Exploring Commercial vs. Open-Source Processors We first investigated available commercial processors. Since our research activities do not result directly in an income that would allow us to pay for regular commercial licenses, we would need to make use of the academic licensing agreements. In all fairness, most processor IP providers had university programmes with reasonable conditions. The problem was that most of these programmes would not allow you to make changes to the architecture, some would need additional licenses for manufacturing actual chips, and most importantly any collaboration we wanted to establish with new partners both from the industry and academia would require additional agreements to be signed that took quite a long time to set up. So we started to look at open source processors. While there was plenty of Verilog and VHDL code available for various processor cores under different licenses, like many readers at the moment, we were not very sure how well these cores were designed and verified, whether or not they were actually used in practice.
* 评估是使用商用的内核，还是开源的处理器？学术研究没有直接收入去支付商用的授权，虽然很多IP处理器有针对学术的授权，但授权的架构无法进行灵活修改，如果做芯片的话还需要额外的授权，还有很大的问题就是任何新的合作伙伴引入，都要重新签署一系列的协议，耗费太久的时间。有很多Verilog和VHDL代码的开源处理器可以授权使用，但这些处理器的质量无法保证。
RISC-V in the PULP Project As an academic institution, we were able to take more risks with our choices and the freedom that an open source processor gives you, both in terms of making enhancements, and in allowing collaboration with anyone without lengthy negotiations about IP ownership was too tempting to pass up. For the first few years, the PULP project used a 32-bit OpenRISC based processor with great success. We were able to improve the performance of our own implementation of OpenRISC cores (called OR10N) to be competitive with state of the art 32-bit processors and these formed the backbone of our successful multi-core systems geared towards ultra-low-power operation.
* 学术研究的好处在于可以在开源架构上有更多灵活性并可以承担风险，比如对架构进行增强，非常灵活、高效地同其他合作伙伴一起研发。作者的团队花了5年时间在他们自己的OpenRisc内核（被称为OR10N）上进行了性能提升，达到与最新的32位处理器相当的性能水平，为超低功耗的多核系统打下了坚实的基础。 Figure 1. The PULP system consists of efficient RISC-V cores, peripherals, interconnect solutions, and accelerators that are combined to create different platforms. RISC-V as a Solution At the same time, we saw how RISC-V ISA was gaining in popularity. By far the most important issue in deciding what processor to use in your projects is the availability of a development environment, preferably with widely known and used tools. No matter how clever you can get with developing your architectures, if you can not get developers to port their applications to your system with ease, you will not get the results you want. In my opinion, it is precisely this point that the RISC-V ISA made the most contribution to the open source hardware community. By maintaining a clear and well thought ISA definition, maintained by the RISC-V foundation (of which ETH Zürich is a founding member), it was possible for a large community to provide ports of compilers and tools to support RISC-V. In the meantime, most of these ports were upstreamed and are available out of the box (for example for GCC since version 7.1 released in April 2017). This is why, early in 2015, we made the switch to RISC-V as well. We were able to use most of the development for our OR10N core and derive our first core implementing the RISC-V ISA called RI5CY and we have continued to use and improve this core over tens of ASICs we have developed throughout the project. We have also adapted RISC-V cores for different use cases, and added specialized cores for applications that have tight resource constraints (Zero/Micro Riscy), as well as adding a 64-bit core called Ariane that is able to boot Linux operating system.
* 使用处理器最关键的是开发环境，基于这方面的考虑，作者的团队在2015年开始切换到Risc V上，并基于过去在OR10N上的积累做成了第一个基于RISC-V ISA的内核称之为RI5CY，并通过项目中做的十几颗ASICs持续提改进内核。他们同时将RISC-V内核用在不同应用场景，并针对一些资源严重受限的应用增加了专用的内核（Zero/Micro Riscy）以及增加了一个64位的内核称之为Ariane，可以启动Linux操作系统。 Figure 2. Our 9-core IoT processor, Mr. Wolf, on a small demonstration board. After slightly more than 5 years on the project, the PULP project has resulted in 26 ASICs (seen in Figure 3 below) that were taped out and tested in various technologies from early trials in mature 180nm technologies all the way down to our latest design called Poseidon realized using Globalfoundries 22nm technology. And we are not done yet, we are currently involved in many projects and collaborations that make use of our PULP technology and will allow us to develop it further. Figure 3. All 26 PULP chips that we have taped out in the last 5 years (not to scale).
* 作者的团队在过去5年的项目中共流片了26个ASICs，从最早的180nm到最新的22nm工艺。 本帖最后由 小飞飞 于 2020-8-10 16:43 编辑
The Reach of Open Source Projects From the beginning, it was clear for us that we would keep PULP project open source, which gives us the flexibility to collaborate with other groups and companies as we see fit and ultimately allows contributions from all over the world. We have adopted the Solderpad Licensing scheme, a derivation of the Apache license introduced by the LowRISC project initiated by the University of Cambridge, which has helped it being adopted for various projects. Our GitHub repository contains the source code for various hardware we have developed as part of the PULP project, not only RISC-V processors, but peripherals (SPI, I2C, GPIO, JTAG) and complete systems form simple microcontrollers, to state-of-the-art multi-core IoT platforms all written in System Verilog. But by far, the most rewarding part of this project has been to experience how well our work was received not only by academia but also in the industry. We learned at the last RISC-V conference in Barcelona, that Google, IBM, and NXP have all evaluated and used our cores and taped out designs based on our work successfully. EDA companies like Cadence and Mentor have used our designs as part of their training and evaluations, and Greenwaves Technologies, a startup from Grenoble in France has based their first product, the GAP8 processor, largely on our multi-core OpenPULP architecture that is available on our GitHub page for everyone. When people speak of open source projects, they often mention that it is free. Most people only take this to mean that you do not pay for it, but the real freedom you get from open source projects is much more and I think more important. People using our RISC-V systems, are free to switch to RISC-V implementations from any other source when they want—after all, the same binaries will work on any RISC-V implementation that follows the standard. Researchers can take what we provide and freely change it for their experiments, knowing full well that the system they are using is not a toy example, but something that also finds applications in real-world scenarios. Startup companies can build on what we provide as a starting point and concentrate their time and energy on the actual innovations they want to provide. People who are disturbed by various attacks on their systems have the chance to look inside and know what exactly is in their system. This may not automatically solve all security issues, but it is an important step towards increased security, by giving a larger community access to scrutinize the system you work with. And yes, all this freedom comes at no extra cost, while there are also commercial RISC-V implementations, our silicon-proven RISC-V systems remain freely accessible over GitHub.
* 作者的团队也将PULP项目开源，所有的代码都在Github上 - RISC-V处理器、SPI/I2C/GPIO/JTAG，从构成一个简单处理器的完整系统到最新技术的多核IoT平台，都有SystemVerilog源码。作者团队的工作和开源精神也获得了学术界和工业界的高度认可 - Google、IBM、NXP都经过评估并采用了他们的内核并做了芯片；Cadence和Mentor Graphic都将这个项目的内核做为培训的案例；法国的创业公司Greenwaves在他们的第一颗商用芯片GAP8中就大幅采用多核OpenPULP架构（这颗用于物联网的低功耗芯片及其开发板在爱板网EEBoard上有评测报告）
开源的好处不仅在与“免费”，而在于你采用这个内核获得的自由度 - 你可以在各种符合标准的RISC-V中进行切换，做教学研究的可以在此基础上进行自由修改；创业公司可以将之作为一个起点进行真正的创新。
RISC-V Benefits in Academia When we started the PULP project 5 years ago, open source hardware was in its infancy. Today, there are still many skeptics, but by judging by the interest of companies both small and large in our project, it has already established itself as a viable alternative and the open collaboration model will surely drive it further. Together with our partners at the University of Bologna, we are very proud of being an active contributor to the RISC-V community and will continue to be a leading supporter of open source hardware in the academia.本篇完
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