E203数据冲突处理OITF

皋陶

流水线的数据冲突分为三类：WAR，RAW，WAW

参考链接：3.3 流水线相关冲突及解决办法_v3.0 https://wenku.baidu.com/view/e066926d48d7c1c708a14508.html

• WAR: write after read 相关性，又称先读后写相关性。比如下面的指令序列，第一条指令会读取x4，第二条指令会写x4。在流水线中，如果第二条指令比第一条指令先写x4，则第一条指令就会读出错误的值。
  

           add x5, x4,x6

           add x4, x3, x2

• WAW: write after write 相关性，又称先写后写相关性。比如下面的指令序列，两条指令都会写x5。在流水线中，如果第二条指令比第一条指令先写x5，就会引起逻辑错误。
  

           add x5, x4,x6

           add x5, x3, x2

• RAW:read after write相关性，又称先写后读相关性。比如下面指令序列，如果第二条指令，在第一条指令写x5之前，第二条指令先读x4，就会引起逻辑错误。
  

           add x5, x4,x6

           add x4, x5, x2

      由于蜂鸟E200系列是按序派遣，按顺序写回的微架构，在指令派遣时候就已经从通用寄存器数组中读取了源操作数。后续执行的指令写回regfile的操作不可能影响到前面指令的读取，所以不可能发生WAR相关性造成的数据冲突。

      正在派遣的指令处在流水线的第二级，假设之前派遣的指令是单周期指令，则前序指令肯定已经完成了执行且将结果写回了Regfile。因此正在派遣的指令不可能会发生RAW数据冲突。但是假设之前派遣的指令是多周期指令(长指令)，由于指令需要多个周期才能写回结果。因此正在派遣的指令可能会产生前序相关的RAW相关性。

     正在派遣的指令处在流水线的第二级，假设之前派遣的指令是单周期指令，则前序指令肯定已经完成了执行且将结果写回了Regfile。因此正在派遣的指令不可能会发生WAW数据冲突。但是假设之前派遣的指令是多周期指令(长指令)，由于指令需要多个周期才能写回结果。因此正在派遣的指令可能会产生前序相关的WAW相关性。

    为了能检测出长指令的RAW和WAW相关性，蜂鸟E200使用了一个outstanding instruction track fifo(OITF)模块。在流水线的派遣(Dispatch)点，每一次派遣一个长指令，则会在OITF中分配一个表项(Entry)，在这个表项中会存储该长指令的结果寄存器索引。在流水线的写回(Write-back)点，每次按顺序写回一个长指令之后，就会将此指令在OITF中的表项移除。

      每条指令派遣时，都会将本指令的源操作数和目的操作数寄存器索引和OITF中的各个表项进行比对，从而判断本指令是否与已经被派遣出，且尚未写回的长指令产生RAW和WAW相关性。如果产生相关性，则stall住当前指令的派遣。如果没有RAW和WAW相关性，且该指令为多周期长指令，把该指令写入OITF，如果OITF是full，则仍要stall住管线，等待OITF释放空间后，再写入并派遣。

   在writeback模块，会进行长指令写回仲裁，长指令写回regfile后，会释放OITF中相应的表项。

OITF代码如下，如果fifo full，则dis_ready=0, 与dispatch模块握手失败，不会发送新的dispatch进来。如果不为空，会发送新的指令进来进行判断。

1. `include "e203_defines.v"
   
2. 
   
3. module e203_exu_oitf (
   
4.   output dis_ready,
   
5. 
   
6.   input  dis_ena, //dispatch a long instruction enable signal
   
7.   input  ret_ena, //write back a long instruction enable signal
   
8. 
   
9.   output [`E203_ITAG_WIDTH-1:0] dis_ptr,  //write pointer
   
10.   output [`E203_ITAG_WIDTH-1:0] ret_ptr,  //read pointer
    
11. 
    
12.   output [`E203_RFIDX_WIDTH-1:0] ret_rdidx,
    
13.   output ret_rdwen,
    
14.   output ret_rdfpu,
    
15.   output [`E203_PC_SIZE-1:0] ret_pc,
    
16. 
    
17.   input  disp_i_rs1en, // enable if current dispatch instruction fetch first source operand  
    
18.   input  disp_i_rs2en, // ...
    
19.   input  disp_i_rs3en, // ...
    
20.   input  disp_i_rdwen, // enable if current dispatch instruction write back to register
    
21.   input  disp_i_rs1fpu, // enable if current dispath instruction need to read float gpr
    
22.   input  disp_i_rs2fpu, //...
    
23.   input  disp_i_rs3fpu, //...
    
24.   input  disp_i_rdfpu,  //enable if current dipatch instruction need to write back to float register files.
    
25.   //register index
    
26.   input  [`E203_RFIDX_WIDTH-1:0] disp_i_rs1idx,
    
27.   input  [`E203_RFIDX_WIDTH-1:0] disp_i_rs2idx,
    
28.   input  [`E203_RFIDX_WIDTH-1:0] disp_i_rs3idx,
    
29.   input  [`E203_RFIDX_WIDTH-1:0] disp_i_rdidx,
    
30.   input  [`E203_PC_SIZE    -1:0] disp_i_pc, //pc of current dispatch instruciotn
    
31. 
    
32.   output oitfrd_match_disprs1, //dispatch instruction rs1 is same as any item of result register in oitf
    
33.   output oitfrd_match_disprs2, //...
    
34.   output oitfrd_match_disprs3, //...
    
35.   output oitfrd_match_disprd,  //dispatch instruction rd is same as any item of result register in oitf.
    
36.   //if empty, no conflict
    
37.   output oitf_empty,
    
38.   input  clk,
    
39.   input  rst_n
    
40. );
    
41. 
    
42.   wire [`E203_OITF_DEPTH-1:0] vld_set;
    
43.   wire [`E203_OITF_DEPTH-1:0] vld_clr;
    
44.   wire [`E203_OITF_DEPTH-1:0] vld_ena;
    
45.   wire [`E203_OITF_DEPTH-1:0] vld_nxt;
    
46.   wire [`E203_OITF_DEPTH-1:0] vld_r; //if it is valid signal in all item
    
47.   wire [`E203_OITF_DEPTH-1:0] rdwen_r;// if it is write back register in all item
    
48.   wire [`E203_OITF_DEPTH-1:0] rdfpu_r; //result register in all item if are float
    
49.   wire [`E203_RFIDX_WIDTH-1:0] rdidx_r[`E203_OITF_DEPTH-1:0]; //register index in all items
    
50.   // The PC here is to be used at wback stage to track out the
    
51.   //  PC of exception of long-pipe instruction
    
52.   wire [`E203_PC_SIZE-1:0] pc_r[`E203_OITF_DEPTH-1:0];
    
53. 
    
54.   wire alc_ptr_ena = dis_ena;  //dispatch a long instruction enable signal, as write pointer enable signal
    
55.   wire ret_ptr_ena = ret_ena;  //write back a long instruction enable signal, as read pointer enable signal
    
56. 
    
57.   wire oitf_full ;
    
58. 
    
59.   wire [`E203_ITAG_WIDTH-1:0] alc_ptr_r; //write pointer, long instruction dispatch
    
60.   wire [`E203_ITAG_WIDTH-1:0] ret_ptr_r; //read pointer, long instruction write back
    
61. 
    
62.   generate
    
63.   if(`E203_OITF_DEPTH > 1) begin: depth_gt1//{
    
64.       //extra mark bit for write full
    
65.       wire alc_ptr_flg_r;
    
66.       wire alc_ptr_flg_nxt = ~alc_ptr_flg_r;
    
67.       wire alc_ptr_flg_ena = (alc_ptr_r == ($unsigned(`E203_OITF_DEPTH-1))) & alc_ptr_ena;
    
68. 
    
69.       sirv_gnrl_dfflr #(1) alc_ptr_flg_dfflrs(alc_ptr_flg_ena, alc_ptr_flg_nxt, alc_ptr_flg_r, clk, rst_n);
    
70. 
    
71.       wire [`E203_ITAG_WIDTH-1:0] alc_ptr_nxt;
    
72.       //if write to fifo depth, write ptr = 0,otherwise write ptr = write ptr + 1
    
73.       assign alc_ptr_nxt = alc_ptr_flg_ena ? `E203_ITAG_WIDTH'b0 : (alc_ptr_r + 1'b1);
    
74. 
    
75.       sirv_gnrl_dfflr #(`E203_ITAG_WIDTH) alc_ptr_dfflrs(alc_ptr_ena, alc_ptr_nxt, alc_ptr_r, clk, rst_n);
    
76. 
    
77.       //extra mark bit for read empty
    
78.       wire ret_ptr_flg_r;
    
79.       wire ret_ptr_flg_nxt = ~ret_ptr_flg_r;
    
80.       wire ret_ptr_flg_ena = (ret_ptr_r == ($unsigned(`E203_OITF_DEPTH-1))) & ret_ptr_ena;
    
81. 
    
82.       sirv_gnrl_dfflr #(1) ret_ptr_flg_dfflrs(ret_ptr_flg_ena, ret_ptr_flg_nxt, ret_ptr_flg_r, clk, rst_n);
    
83. 
    
84.       wire [`E203_ITAG_WIDTH-1:0] ret_ptr_nxt;
    
85.       //if read to fifo depth, read ptr = 0, otherwise read prt = read prt + 1
    
86.       assign ret_ptr_nxt = ret_ptr_flg_ena ? `E203_ITAG_WIDTH'b0 : (ret_ptr_r + 1'b1);
    
87. 
    
88.       sirv_gnrl_dfflr #(`E203_ITAG_WIDTH) ret_ptr_dfflrs(ret_ptr_ena, ret_ptr_nxt, ret_ptr_r, clk, rst_n);
    
89.       //empty, full mark
    
90.       assign oitf_empty = (ret_ptr_r == alc_ptr_r) &   (ret_ptr_flg_r == alc_ptr_flg_r);
    
91.       assign oitf_full  = (ret_ptr_r == alc_ptr_r) & (~(ret_ptr_flg_r == alc_ptr_flg_r));
    
92.   end//}
    
93.   else begin: depth_eq1//}{
    
94.       assign alc_ptr_r =1'b0;
    
95.       assign ret_ptr_r =1'b0;
    
96.       assign oitf_empty = ~vld_r[0];
    
97.       assign oitf_full  = vld_r[0];
    
98.   end//}
    
99.   endgenerate//}
    
100. 
     
101.   assign ret_ptr = ret_ptr_r;
     
102.   assign dis_ptr = alc_ptr_r;
     
103. 
     
104. ////
     
105. //// // If the OITF is not full, or it is under retiring, then it is ready to accept new dispatch
     
106. //// assign dis_ready = (~oitf_full) | ret_ena;
     
107. // To cut down the loop between ALU write-back valid --> oitf_ret_ena --> oitf_ready ---> dispatch_ready --- > alu_i_valid
     
108. //   we exclude the ret_ena from the ready signal
     
109. assign dis_ready = (~oitf_full);
     
110. 
     
111.   wire [`E203_OITF_DEPTH-1:0] rd_match_rs1idx;
     
112.   wire [`E203_OITF_DEPTH-1:0] rd_match_rs2idx;
     
113.   wire [`E203_OITF_DEPTH-1:0] rd_match_rs3idx;
     
114.   wire [`E203_OITF_DEPTH-1:0] rd_match_rdidx;
     
115. 
     
116.   genvar i;
     
117.   generate //{
     
118.       for (i=0; i<`E203_OITF_DEPTH; i=i+1) begin:oitf_entries//{
     
119.         //every time, assign a item and write pointer same as current i, then
     
120.         //valid set is high
     
121.         assign vld_set[i] = alc_ptr_ena & (alc_ptr_r == i);
     
122.         //every time, assign a item and read pointer same as current i, then
     
123.         //valid clr is high
     
124.         assign vld_clr[i] = ret_ptr_ena & (ret_ptr_r == i);
     
125.         assign vld_ena[i] = vld_set[i] |   vld_clr[i];
     
126.         assign vld_nxt[i] = vld_set[i] | (~vld_clr[i]);
     
127. 
     
128.         sirv_gnrl_dfflr #(1) vld_dfflrs(vld_ena[i], vld_nxt[i], vld_r[i], clk, rst_n);
     
129.         //Payload only set, no need to clear
     
130.         sirv_gnrl_dffl #(`E203_RFIDX_WIDTH) rdidx_dfflrs(vld_set[i], disp_i_rdidx, rdidx_r[i], clk);
     
131.         sirv_gnrl_dffl #(`E203_PC_SIZE    ) pc_dfflrs   (vld_set[i], disp_i_pc   , pc_r[i]   , clk);
     
132.         sirv_gnrl_dffl #(1)                 rdwen_dfflrs(vld_set[i], disp_i_rdwen, rdwen_r[i], clk);
     
133.         sirv_gnrl_dffl #(1)                 rdfpu_dfflrs(vld_set[i], disp_i_rdfpu, rdfpu_r[i], clk);
     
134.         //compare dispatch source operand with result register in fifo
     
135.         assign rd_match_rs1idx[i] = vld_r[i] & rdwen_r[i] & disp_i_rs1en & (rdfpu_r[i] == disp_i_rs1fpu) & (rdidx_r[i] == disp_i_rs1idx);
     
136.         assign rd_match_rs2idx[i] = vld_r[i] & rdwen_r[i] & disp_i_rs2en & (rdfpu_r[i] == disp_i_rs2fpu) & (rdidx_r[i] == disp_i_rs2idx);
     
137.         assign rd_match_rs3idx[i] = vld_r[i] & rdwen_r[i] & disp_i_rs3en & (rdfpu_r[i] == disp_i_rs3fpu) & (rdidx_r[i] == disp_i_rs3idx);
     
138.         assign rd_match_rdidx [i] = vld_r[i] & rdwen_r[i] & disp_i_rdwen & (rdfpu_r[i] == disp_i_rdfpu ) & (rdidx_r[i] == disp_i_rdidx );
     
139. 
     
140.       end//}
     
141.   endgenerate//}
     
142.   //rs1 in fifo, so RAW relative
     
143.   assign oitfrd_match_disprs1 = |rd_match_rs1idx;
     
144.   //rs2 in fifo, so RAW relative
     
145.   assign oitfrd_match_disprs2 = |rd_match_rs2idx;
     
146.   //rs3 in fifo, so RAW relative
     
147.   assign oitfrd_match_disprs3 = |rd_match_rs3idx;
     
148.   //rd in fifo, so WAW relative
     
149.   assign oitfrd_match_disprd  = |rd_match_rdidx ;
     
150. 
     
151.   assign ret_rdidx = rdidx_r[ret_ptr];
     
152.   assign ret_pc    = pc_r [ret_ptr];
     
153.   assign ret_rdwen = rdwen_r[ret_ptr];
     
154.   assign ret_rdfpu = rdfpu_r[ret_ptr];
     
155. 
     
156. endmodule

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